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DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter General Description
The DM9301 is a physical-layer, single-chip, lowpower media converter for 100BASE-TX/FX full duplex repeater applications. On the TX media side, it provides a direct interface to Unshielded Twisted Pair Cable 5 (UTP5) for 100BASE-TX Fast Ethernet. On the FX media side, it provides a direct interface to a Pseudo Emitter Coupled Logic level interface (PECL). The DM9301 uses a low power and high performance CMOS process. It contains the entire physical layer functions of 100BASE-TX as defined by IEEE802.3u, including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD) and a PECL compliant interface for a fiber optic module, compliant with ANSI X3.166. The DM9301 provides two independent clock recovery circuits to minimize bit delay through the converter (no FIFO are used to buffer data between the FX and TX interfaces). Furthermore, due to the excellent rise/fall time control by a built-in waveshaping filter, the DM9301 needs no external filter to transport signals to the media on the 100Base-TX interface.
Patent-Pending Circuits * * * Smart adaptive receiver equalizer Digital algorithm for high frequency clock/data recovery circuit High speed wave-shaping circuit
Block Diagram
PECLSD
FXSD RCVR 25M FXRXCLK 125M FXRXCLK
Link Status Monitor & LED Driver Rise/Fall Time CTL
PECLRXI +/-
PECL RCVR RX CRM
NRZI to NRZ
Serial to Parallel
Scrambler
Parallel to Serial
NRZ to NRZI
NRZI to MLT-3
MLT-3 Driver
TPTXO+/-
TX Codegroup Alignment Monitor 25M OSC/XTAL CGM
FX Codegroup Alignment Monitor
25M TPRXCLK 125M TPRXCLK
PECLTXO +/-
PECL TXMT
NRZ to NRZI
Parallel to Serial
Descrambler
Serial to Parallel
NRZI to NRZ RX CRM
MLT-3 to NRZI
Adaptive EQ
TPRXI+/-
Final Version: DM9301-DS-F02 May 8, 2000
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DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Table of Contents
Block Diagram ........................................................1 Table of contents ....................................................2 Features .................................................................3 Pin Configuration: DM9301 QFP .............................4 Pin Description .......................................................5 Functional Description ..........................................10 100Base-FX to TX Operation ................................10 FX PECL Receiver ............................................10 FX Receiver Clock Recovery Module ................10 FX NRZI to NRZ Converter ...............................10 FX Serial to Parallel Converter ..........................11 FX Code Group Alignment Monitor ....................11 TX Scrambler ....................................................11 TX Parallel to Serial Converter ..........................11 TX NRZ to NRZI Converter ...............................11 TX NRZI to MLT-3 Converter.............................11 TX MLT-3 Driver ...............................................11 100Base-TX to FX Operation ................................12 TX Signal Detect ...............................................12 TX Digital Adaptive Equalization........................12 TX MLT-3 to NRZI Decoder...............................13 TX Clock Recovery Module ...............................13 TX NRZI to NRZ Decoder..................................13 TX Serial to Parallel Converter ..........................13 TX Code Group Monitor ....................................13 TX Descrambler ................................................13
2
T T T T T T T
General Description ................................................1
FX Parallel to Serial Converter .......................... 13 FX NRZ to NRZI Encoder ................................. 13 Link Monitor and LED Driver ............................. 13
Absolute Maximum Ratings .................................. 14 DC Electrical Characteristics ................................ 15 AC Electrical Characteristics................................. 16 Timing Waveforms ............................................... 17 100BASE-TX to FX Transmit Timing Diagram ... 17 100BASE-FX to TX Transmit Timing Diagram ... 17 5-Bit Symbol 100Base-TX/FX Transmit Timing Diagram ............................................................ 17 5-Bit Symbol 100Base-TX/FX Receive Timing Diagram ............................................................ 18 Application Circuit (For Reference Only) ............... 19 Package Information............................................. 21 Ordering Information............................................. 22 Disclaimer ............................................................ 22 Company Overview .............................................. 22 Products............................................................... 22 Contact Windows.................................................. 22 Warning ............................................................... 22
T T T T T T T T
T T T T T T T T T T
Final Version: DM9301-DS-F02 May 8, 2000
DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Features
* 100BASE-TX/FX single-chip media converter * Total bit delay from FX to TX interface is 20 bit times (10 bit times each direction). * Optional propagate HALT on no Link condition * Compliant with IEEE802.3u 100BASE-TX standard * Compliant with ANSI X3T12 TP-PMD 1995 standard * Compliant with ANSI X3.166 FDDI-PMD * Supports Half and Full Duplex operation 100Mbps, the DM9301 operates in Full Duplex mode at all times * High performance 100Mbps clock generator and data recovery circuit * Controlled output edge rates in the 100Base-TX transmitter without the need for an external filter * LED support for FX Link, TX link, FX receive data, TX receive data, FX code group error and TX code group error. * Built in LED test, all LED will light during a reset condition on the DM9301 * Digital clock recovery and regeneration circuit using an advanced digital algorithm to minimize jitter * Supports diagnostic TX to TX analog loopback and FX to FX analog loopback (Loopback at the NRZI interface) * Supports diagnostic TX to TX digital loopback and FX to FX digital loopback (Loopback at the 5B symbol interface) * Low-power, high-performance CMOS process * Available in a 100 QFP package
Final Version: DM9301-DS-F02 May 8, 2000
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DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Pin Configuration: DM9301F QFP
TXDLPBK
TESTMODE
FXDLPBK
CONFIGB
CONFIGA
RESET#
TRIDRV
TPMUX
DGND
DGND
DGND 82
AGND
AGND
DVCC
DVCC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
TPRXI+ TPRXIAVCC AVCC AGND AGND AVCC BGREF BGRET AVCC AGND AGND TPTXOTPTXO+ AVCC AGND AGND PECLTXOPECLTXO+ AGND AVCC PECLSDPECLSD+ PECLRXIPECLRXI+ AVCC OSC/X1 X2 AGND OSC/XTL#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
81 80 79 78 77 76 75 74 73 72 71 70 69 68 67
DVCC
TPI3
TPI2
TPI1
TPI0
FXERRLED# RXD0 DGND RXD1 RXD2 DVCC RXD3 RXD4 DGND TXCLK RXCLK FXRCVLED# DGND FXLNKLED# DVCC TPO6 TXLNKLED# DGND TXRCVLED# TPO0 TPO1 DGND TPO2 TPO3 DVCC TPO4 TPO5 DGND TXERRLED# DVCC
DM9301F
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
AGND
FXALPBK
DGND
AVCC
MUXCTL1
MUXCTL0
TXALPBK
BPSCRAM
HLTNOLNK
TPEN
TXD1
FRCFXSD
DVCC
TXD4
TXD3
TXD2
TXD0
DGND
4
DGND
DVCC
Final Version: DM9301-DS-F02 May 8, 2000
DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Pin Description
Pin No. Media Interface 1, 2 Pin Name TPRXI+, TPRXII/O I Description 100Mbps-TX Differential Input Pair: These pins are differential receive input for 100BASETX. They are capable of receiving 100BASE-TX MLT-3 data. 100BASE-TX Differential Output Pair: These outputs drive MLT-3 encoded data over 100Mbps twisted pair cable and provide controlled rise and fall times designed to filter the transmitter output, reducing any associated EMI. 100BASE-FX PECL Receive Data Differential Pair: These pins are differential receive input for 100BASEFX PECL. They are capable of receiving PECL 100BASE-FX NRZI data. 100BASE-FX Transmit Differential Output Pair: These outputs drive NRZI encoded data for PECL FX interface. 100BASE-FX PECL Signal detect: These pins are differential signals that indicate to the DM9301 that the Optical Module interface is detecting valid optical energy. Crystal or Oscillator Input: This pin should connect to one side of a 25MHz, 50ppm crystal if OSC/XTL#=0. This pin is the 25MHz, 50ppm external TTL oscillator input, if OSC/XTLB=1. Crystal Oscillator Output: The other side of a 25MHz, 50ppm crystal should connect to this pin if OSC/XTL#=0. Leave this pin open if OSC/XTL#=1. Crystal or Oscillator Selector Pin: OSC/XTL#=0: An external 25MHz, 50ppm crystal should connect to X1 and X2 pins. OSC/XTL#=1: An external 25MHz, 50ppm oscillator should connect to X1 and left X2 pin open. Bandgap Voltage Reference Resistor: It connects to a 6.49K, 1% error tolerance resistor between this pin and BGRET pin 9 to provide an accurate current reference for the chip. Bandgap Return Return pin for 6.49K resistor connection, DO NOT CONNECT TO GROUND.
13, 14
TPTXO-, TPTXO+
O
24, 25
PECLRXI-, PECLRXI+
I
18, 19
PECLTXO-, PECLTXO+ PECLSD-, PECLSD+
O
22, 23
I
Clock and Misc. Interface 27 OSCI/X1
I
28
X2
O
30
OSC/XTL#
I
8
BGREF
I
9
BGRET
I
Final Version: DM9301-DS-F02 May 8, 2000
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DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
Clock and Misc. Interface (Continued) 84 TRIDRV
I
85 34
RESET# HLTNOLNK
I I
93 95 LED Interface 67
CONFIGA CONFIGB FXLNKLED#
I I OD
Tristate Digital Output Pins: When set high, all digital output pins are set to high impedance. Reset: Active Low input that initializes the DM9301, must be asserted low for 30msecs after VCC is stable. Send Halt on no Link Condition: Causes the DM9301 to Send out a Halt symbol to the TX interface if no FX link active or send out a Halt symbol to the FX interface if no TX link active. Propagates a no-link condition to the Link Partner if 1, Idle symbol if 0. Active high Config A: Must be connected to GND Config B: Must be connected to GND FX Link LED: Indicates Good Link status for 100Mbps FX operation. Active low (Open Drain Output) TX Link LED: Indicates Good Link status for 100Mbps TX operation. Active low (Open Drain Output) FX Receive LED: Indicates the presence of receive activity for 100Mbps FX operation. Active low (Open Drain Output) The DM9301 incorporates a "monostable" function on the FXRCVLED output. This ensures that even minimum size packets generate adequate LED ON to insure visibility. TX Receive LED: Indicates the presence of receive activity for 100Mbps TX operation. Active low (Open Drain Output) The DM9301 incorporates a "monostable" function on the TXRCVLED output. This ensures that even minimum size packets generate adequate LED ON to insure visibility. FX Error LED: Indicates an error was detected by the FX Code Group Alignment Monitor function on the FX receiver. Active low (Open Drain Output) The DM9301 incorporates a "monostable" function on the FXERRLED output. This ensures that even minimum size errors generate adequate LED ON to insure visibility.
64
TXLNKLED#
OD
69
FXRCVLED#
OD
62
TXRCVLED#
OD
80
FXERRLED#
OD
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Final Version: DM9301-DS-F02 May 8, 2000
DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
LED Interface(Continued) 52 TXERRLED#
OD
TX Error LED: Indicates an error was detected by the TX Code Group Alignment Monitor function on the TX receiver. Active low (Open Drain Output) The DM9301 incorporates a "monostable" function on the TXERRLED output. This ensures that even minimum size errors generate adequate LED ON to insure visibility. FX Interface Analog Loop Back: Loops the FX NRZI analog transmit data path to the FX NRZI analog receive path. Initiated at a H/W reset. Active high. TX Interface Analog Loop Back: Loops the TX NRZI analog transmit data path to the TX NRZI analog receive path. Initiated at a H/W reset. Active high. FX Interface Digital Loop Back: Loops the FX 5-bit symbol digital transmit data path to the FX 5-bit symbol digital receive path. Initiated at a H/W reset. Active high. TX Interface Digital Loop Back: Loops the TX 5-bit symbol digital transmit data path to the TX 5-bit symbol digital receive path. Initiated at a H/W reset. Active high. Receive Data 4 through 0: The receive data 5-bit symbol interface. Data is clocked out on the falling edge of RXCLK. Receive Clock: 25 Mhz recovered clock, clock source is selected by the MUXCTL1 and MUXCTL0. Transmit Data 4 through 0: The transmit data 5-bit symbol interface. Data is clocked in on the rising edge of TXCLK. Transmit Clock: 25 Mhz recovered clock, clock source is selected by the MUXCTL1 and MUXCTL0.
Diagnostic Port Interface 36 FXALPBK
I
35
TXALPBK
I
96
FXDLPBK
I
97
TXDLPBK
I
79, 77, 76, 74, 73 70
RXD0, RXD1, RXD2, RXD3, RXD4 RXCLK
0
O
48, 47, 45, 44, 43 71
TXD0, TXD1, TXD2, TXD3, TXD4 TXCLK
I
O
Final Version: DM9301-DS-F02 May 8, 2000
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DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
Diagnostic Port Interface (Continued) 39, 40 MUXCTL1, MUXCTL0
I
Mux. Control 1 and 0: Used for testing the DM9301 Data Paths. Set to zero for normal operation. Initiated at a H/W reset. Active high. DATA PATH MUXCTL1 MUXCTL0 0 0 Normal, FX to TX and TX to FX 1 0 TX Transmit from TXD[4:0] TXCLK from TX PLL TX Receive to RXD[4:0] RXCLK from TX receive clock FX Transmit from TXD[4:0] TXCLK from FX PLL FX Receive to RXD[4:0] RXCLK from FX receive clock TX Transmit from TXD[4:0] TXCLK from TX PLL FX Receive to RXD[4:0] RXCLK from FX receive clock
0
1
1
1
65, 54, 55, 57, 58, 60, 61 92, 91, 89, 88
TPO6, TPO5, TPO4, TPO3, TPO2, TPO1, TPO0 TPI3, TPI2, TPI1, TPI0,
O
I
Test Port Output: Reflects the DM9301 internal status. Selection of status indicators is made by using TPEN and TPMUX. Initiated at a H/W reset. Active high. Test Port Input: Controls the DM9301 internal test features. Selection of input control is made by using TPEN and TPMUX. TPEN must be true (one) for this signal to take effect. Initiated at a H/W reset. Active high.
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Final Version: DM9301-DS-F02 May 8, 2000
DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
Diagnostic Port Interface (Continued) 49 FRCFXSD
I
38
TPEN
I
87
TPMUX
I
41
BPSCRAM
I
Force FX Signal Detect Forces the DM9301 FX interface Signal Detect true Initiated at a H/W reset. Active high. Test Port Enable: Enables the DM9301 Test Port features. Initiated at a H/W reset. Active high. Test Port Mux: Controls the DM9301 Test Port Input and Output bits. A value of zero indicates the TX interface and a value of one indicates the FX interface. TPEN must be true (one) for this signal to take effect. Initiated at a H/W reset. Active high. Bypass Scrambler: Controls the DM9301 TX interface Scrambler/Descrambler function. A value of zero indicates to scramble and de-scramble the TX interface 5-bit symbol data to and from the FX interface. A value of one bypasses the scrambler/de-scrambler function. Initiated at a H/W reset. Active high.
Power and Ground Pins : The power (VCC) and ground (GND) pins of the DM9301 are grouped in pairs of two categories - Digital Circuitry Power/Ground Pairs and Analog Circuitry Power/Ground Pair. Group A - Digital Supply Pairs 33, 42, 50, 53, 63, 68, 82, 90, 98 37, 46, 51, 66, 81, 94 DGND P Digital Logic Ground.
DVCC
P
Digital Logic power supply
Group B - Analog Circuit Supply Pairs 5, 6, 11, 12, 20, 29, 32, 99, 100, 3, 4, 7, 15, 21, 26, 31 AGND AVCC P P Analog circuit ground Analog circuit power supply
Final Version: DM9301-DS-F02 May 8, 2000
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DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Functional Description
The DM9301 Fast Ethernet single-chip TX/FX media converter, provides the functionality as specified in IEEE802.3, integrates the complete 100BASE-TX and a PECL optic module interface for 100Base-FX. The DM9301 implements the PCS, PMA, and TP-PMD sublayer functions, as defined by specification. The term "X" will be used to describe the sections used in the fiber PHY layer interface. The term "X" will be used to describe the sections used in the twisted-pair PMD layer interface. 100BASE-FX to TX Operation The block diagram in figure 1 provides an overview of the functional blocks contained in the FX to TX media converter interface. The FX to TX interface includes the following functional blocks: * * * * * * * * * * FX PECL Receiver FX Receiver Clock Recovery Module FX NRZI to NRZ Converter FX Serial to Parallel Converter FX Code Group Alignment Monitor TX Scrambler TX Parallel to Serial Converter TX NRZ to NRZI Converter TX NRZI to MLT-3 Converter TX MLT-3 Driver
FXSD RCVR 25M FXRXCLK 125M FXRXCLK FX Link Status Monitor Rise/Fall Time CTL
FX PECL Receiver The PECL receiver receives NRZI encoded, differential Pseudo Emitter Coupled Logic level signal. The receiver converts the receive signal into a single-ended NRZI signal and presents this signal to the FX Clock Recovery Module. FX Receiver Clock Recovery Module The FX Clock Recovery Module accepts NRZI data from the PECL receiver. The FX Clock Recovery Module locks onto the data stream, using a Phase Lock Loop (PLL) and extracts the 125Mhz reference clock. The extracted and synchronized clock and data are presented to the FX NRZI to NRZ Decoder. FX NRZI to NRZ Converter The receive data stream is required to be NRZI encoded for compatibility with the standards for 100Base- FX. This conversion process must be reversed on the transmit end. The FX NRZI to NRZ decoder, receives the NRZI data stream from the FX Clock Recovery Module and converts it to a NRZ data stream to be presented to the FX Serial to Parallel conversion block.
PECLSD
PECLRXI +/-
FX PECL RCVR
FX RX CRM
FX NRZI to NRZ
FX Serial to Parallel
TX Scrambler
TX Parallel to Serial
TX NRZ to NRZI
TX NRZI to MLT-3
MLT-3 Driver
TPTXO+/-
FX Codegroup Alignment Monitor 25M OSC/XTAL CGM
FX to TX Block Diagram Figure 1
10 Final Version: DM9301-DS-F02 May 8, 2000
DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
FX Serial to Parallel Converter The Serial to Parallel converter receives a serial data stream from the NRZI to NRZ converter, and converts the data stream to parallel data to be presented to the scrambler. The parallel data format presented to the TX scrambler is 5B coded. TX Parallel to Serial Converter The TX Parallel to Serial converter receives parallel 5B scrambled data from the scrambler and serializes it (converts it from a parallel to a serial data stream). The serialized data stream is then presented to the NRZ to NRZI converter block
FX Code Group Alignment Monitor The FX Code Group Alignment block receives nonaligned 5B data from the FX Serial to Parallel converter and monitors it for 5B code group violations. FX Code Group Alignment occurs after the J/K is detected, and subsequent data is monitored on a fixed boundary. If a violation is detected, the FX Code Group Alignment Monitor block signals the error to the Link Status Monitor block. In turn, the Link Status Monitor block flashes the FX error LED (FXERRLED#).
TX NRZ to NRZI Converter After the transmit data stream has been scrambled and serialized, the data must be NRZI encoded for compatibility with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded twisted pair cable.
TX MLT-3 Converter The MLT-3 conversion is accomplished by converting the data stream output from the NRZI encoder into two binary data streams with alternately phased logic one events.
TX Scrambler The scrambler also receives data from the FX Serial to Parallel converter. Data from the serial to parallel conversion block is 5B symbol encoded. The scrambler is required to control the radiated emissions (EMI) by spreading the transmit energy across the frequency spectrum at the media connector and on the twisted pair cable in 100BaseTX transmit operation. By scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency range. Without the scrambler, energy levels on the cable could peak beyond FCC limitations at frequencies related to repeated 5B sequences like continuous transmission of IDLE symbols. The scrambler output is combined with the NRZ 5B data from the FX Serial to Parallel converter via an XOR logic function. The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at critical frequencies.
TX MLT-3 Driver The two binary data streams created at the MLT-3 converter are fed to the twisted pair output driver which converts these streams to current sources and alternately drives either side of the transmit transformer primary winding resulting in a minimal current MLT-3 signal.
Final Version: DM9301-DS-F02 May 8, 2000
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DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
100Base-TX to FX Operation The block diagram in figure 2 provides an overview of the functional blocks contained in the TX to FX media converter interface. The TX to FX interface contains the following functional blocks: * * * * * * * * * * TX Digital Adaptive Equalization TX MLT-3 to NRZI TX Clock Recovery Module TX NRZI to NRZ Decoder TX Serial to Parallel Conversion TX Descrambler TX Code Group Alignment Monitor FX Parallel to Serial Conversion FX NRZ to NRZI FX PECL Transmitter TX Digital Adaptive Equalization When transmitting data at high speeds over copper twisted pair cable, attenuation based on frequency becomes a concern. In high speed twisted pair signaling, the frequency content of the transmitted signal can vary greatly during normal operation based on the randomness of the scrambled data stream. This variation in signal attenuation caused by frequency variations must be compensated for to ensure the integrity of the received data. In order to ensure quality transmission when employing MLT-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. The selection of long cable lengths for a given implementation, requires significant compensation which will be over-kill in a situation that includes shorter, less attenuating cable lengths. Conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables.
TX Signal Detect The signal detect function meets the specifications mandated by the ANSI XT12 TP-PMD100Base-TX standards for both voltage thresholds and timing parameters.
TX Link Status Monitor
TX Codegroup Alignment Monitor 25M OSC/XTAL CGM
25M TPRXCLK 125M TPRXCLK TX NRZ to NRZI TX NRZI to NRZ
PECLTXO +/-
TX PECL TXMT
FX Parallel to Serial
TX Descrambler
TX Serial to Parallel
TX MLT-3 to NRZI TX CRM
TX Adaptive EQ
TPRXI+/-
TX to FX Block Diagram Figure 2
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Final Version: DM9301-DS-F02 May 8, 2000
DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
Therefore, the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length. TX MLT-3 to NRZI Decoder The DM9301 decodes the MLT-3 information from the TX Digital Adaptive Equalizer into NRZI data. TX Clock Recovery Module The TX Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The TX Clock Recovery Module locks onto the data stream and extracts the 125Mhz reference clock. The extracted and synchronized clock and data are presented to the NRZI to NRZ Decoder. TX NRZI to NRZ Decoder The TX transmit data stream is required to be NRZI encoded in for compatibility with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded twisted pair cable. This conversion process must be reversed on the receive end. The NRZI to NRZ decoder, receives the NRZI data stream from the TX Clock Recovery Module and converts it to a NRZ data stream to be presented to the TX Serial to Parallel conversion block. TX Serial to Parallel Converter The TX Serial to Parallel converter receives a serial data stream from the TX NRZI to NRZ decoder, and converts the data stream to parallel data to be presented to the TX descrambler. The parallel data format presented to the TX descrambler is 5B coded. TX Code Group Monitor The TX Code Group Alignment block receives nonaligned 5B data from the TX descrambler and monitors it for 5B code group violations. TX Code Group Alignment occurs after the J/K is detected, and subsequent data is monitored on a fixed boundary. If a violation is detected, the TX Code Group Monitor block signals the error to the Link Status Monitor block. In turn, the Link Status Monitor block flashes the TX error LED (TXERRLED#). TX Descrambler Because of the scrambling process required to control the radiated emissions of transmit data streams, the receiver must descramble the receive data streams. The TX Descrambler receives scrambled parallel data streams from the Serial to Parallel converter, descrambles the data streams, and presents the data streams to the Code Group alignment block. FX Parallel to Serial Converter The FX Parallel to Serial Converter receives parallel 5B data from the TX de-scrambler and serializes it (converts it from a parallel to a serial data stream). The serialized data stream is then presented to the FX NRZ to NRZI Encoder block FX NRZ to NRZI Encoder After the transmit data stream has been serialized, the data must be NRZI encoded for compatibility with the standard for 100Base-FX. Link Monitor and LED Driver The Link Monitor block monitors both the TX and FX interfaces for link active, receive data and erring 5-bit stream. The Link Monitor has the ability to detect each interfaces link status. The TX will transmit either an Idle symbol or a Halt symbol if the FX link is not established. Conversely the FX will transmit either an Idle symbol or a Halt symbol if the TX link is not established. When an o Link" condition exists, the interface pin called LTNOLNK" will cause Halt symbols to be transmitted instead of Idle symbols. The link active LED is a static indication of the TX and FX links. It will be true to indicate the presence of a link. The receive data and error LED are generated through a ne-Shot" so that even the smallest receive or error condition will be indicated.
Final Version: DM9301-DS-F02 May 8, 2000
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DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Absolute Maximum Ratings*
Absolute Maximum Ratings ( 25C ) Symbol Parameter VCC Max. Supply Voltage VIN DC Input Voltage (VIN) VOUT DC Output Voltage(VOUT) Tstg Storage Temperature Rang (Tstg) PD Power Dissipation (PD) LT Lead Temp. (TL, Soldering, 10 sec.) ESD ESD rating (Rzap=1.5K,Czap=100pF)
Min. --0.5 -0.5 -65 -------
Max. 7.0 5.5 5.5 +150 1 240 4000
Unit V V V C W C V
Conditions Non-operating
Operating Conditions Symbol Parameter DVCC,AVCC Supply Voltage Tc Case Temperature PD 100BASE-TX
(Power Dissipation)
Min. 4.75 0 ---
Max. --85 200
Unit 5.25 C mA
Conditions
5V
*Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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Final Version: DM9301-DS-F02 May 8, 2000
DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter DC Electrical Characteristics (VCC = 5V)
Symbol Parameter Min. TTL Inputs (DPLXSEL, RESET# ) VIL Input Low Voltage VIH Input High Voltage 2.0 IIL Input Low Current -200 IIH Input High Current LED Driver Outputs (FXLINKLED#, TXLINKLED#, FXRXD#,RXRXD#) VOL Output Low Voltage VOH Output High Voltage 2.4 TPTX Receiver VICM RXI+/RXI- Input Common-Mode 1.5 Voltage TPTX Transmitter ITD100 100TXO+/- 100BASE-TX Mode Differential Output Current PECL FX Transmitter IFD100 PECLTX+/- 100BASE-FX Mode Differential Output Current VOH VOL PECL Output Voltage - High PECL Output Voltage - Low VCC1.05 VCC1.81 Typ. Max. Unit Conditions
0.8
100
V V uA uA
IIL = -400uA IIH = 100uA VIN = 0.4V VIN = 2.7V
0.4
V V V
IOL = 8mA IOH = -0.1mA 100 Termination Across
2.0
2.5
mA
mA VCC0.88 VCC1.62 V V
Final Version: DM9301-DS-F02 May 8, 2000
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DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter AC Electrical Characteristics (Over full range of operating condition unless specified otherwise)
Symbol Parameter Transmitter tTR/F 100TXO+/- Differential Rise/Fall Time tTM 100TXO+/- Differential Rise/Fall Time Mismatch tTDC 100TXO+/- Differential Output Duty Cycle Distortion tT/T 100TXO+/- Differential Output Peak-toPeak Jitter XOST 100TXO+/- Differential Voltage Overshoot PECL Transmitter (FX Transmit Interface) ptTR/F 100FXTD+/- Differential Rise/Fall Time ptTM 100FXTD+/- Differential Rise/Fall Time Mismatch ptTDC 100FXTD+/- Differential Output Duty Cycle Distortion ptPPJ 100FXTD+/- Differential Output Peak-toPeak Jitter ptDDJ 100FXTD+/- Differential Output Data Dependent Jitter Clock Specifications XNTOL TX Input Clock Frequency Tolerance (Oscillator or Crystal input frequency) XBTOL TX Output Clock Frequency Tolerance tPWH OSC Pulse Width High tPWL OSC Pulse Width Low tRPWH RX_CLK Pulse Width High tRPWL RX_CLK Pulse Width Low Min. 3.0 -0.5 -0.5 300 5 1.0 -0.5 -0.5 2.0 0.5 0.5 300 2.0 Typ. Max. 5.0 0.5 0.5 Unit ns ns ns ps % ns ns ns ps ns Conditions
-50 -100 14 14 14 14
+50 +100
ppm ppm ns ns ns ns
25MHz Frequency 25MHz Frequency
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Preliminary Version: DM9301-DS-F02 May 8, 2000
DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Timing Waveforms
100BASE-TX to FX Transmit Timing Diagram
TPRXI+/tFX pd PECLTX+/-
100BASE-TX to FX Transmit Timing Parameters Symbol tFXpd Parameter TPRXI+/- to PECLTX+/- Out (FX Latency) Min. Typ1. Max. 10 Unit BT Conditions
100BASE-FX to TX Transmit Timing Diagram
PECLTX+/tTX pd TPRXI+/-
100BASE-FX to TX Transmit Timing Parameters Symbol tTXpd Parameter PECLRX+/- to TPTXo+/- Out (TX Latency) Min. Typ1. Max. 10 Unit BT Conditions
5-Bit Symbol 100Base-TX/FX Transmit Timing Diagram
TXCLK tTX S TXD [4:0] tTX h
100TX+/100FX+/-
tTXD pdtpo
tTXD pdfxo
tTX rft
Final Version: DM9301-DS-F02 May 8, 2000
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DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
5-Bit Symbol 100Base-TX/FX Transmit Timing Parameters Symbol tTXs tTXh tTXDpdtpo tTXDpdfxo tTXr/f Parameter TXD[4:0] Setup To TX_CLK High TXD[4:0] Hold From TX_CLK High TXD[4:0] Sampled To TPTXO (TXD to TP Latency) TXD[4:0] Sampled To PECLTXO (TXD to FX Latency) 100TX Driver Rise/Fall Time Min. 11 0 3 Typ.1 4 Max. 6 4 5 Unit ns ns BT BT ns 90% To 10%, Into 100ohm Differential Conditions
1. Typical values are at 25and are for design aid only; not guaranteed and not subject to production testing.
5-Bit Symbol 100Base-TX/FX Receive Timing Diagram
RXCLK tRX S tRX h RXD [4:0] tR X D pdtxi TX RXI+/FX RXI+/tR X D pdfxi
5-Bit Symbol 100Base-TX/FX Receive Timing Parameter Symbol tRXs tRXh tRXDpdtxi tRXDpdfxi Parameter RXD[4:0) Setup To RX_CLK High RXD[4:0]Hold From RX_CLK High TXRXI In To RXD[0:3] Out (Rx Latency) PECLRDI In To RXD[4:0] Out (Rx Latency) Min. 10 10 Typ1. Max. 6 4 Unit ns ns BT BT Conditions
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Preliminary Version: DM9301-DS-F02 May 8, 2000
DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter MII Application Circuit: DM9301 QFP (For Reference Only)
DM9301 Sample,
suggested placement
Fiber LEDs .125 J1 Power Jack
.120
Twisted LEDs
100 PIN QFP SOT-223 3.3v REG .080 holes with Plating .018 holes
PIN 1
U1
.80
J2
PE68551 LAN Xformer
PIN 1 PIN 1
RJ45
Footprints for either Optical module
0.25 in
.120 Holes
0.80 inch
CUT AWAY POWER PLANE IN THIS AREA (See Schematic ) THIS IS A ISOLATION BARRIER
.350
Final Version: DM9301-DS-F02 May 8, 2000
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DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter MII Application Circuit: DM9301 QFP (Continued, For Reference Only)
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Preliminary Version: DM9301-DS-F02 May 8, 2000
DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Package Information
QFP 100L Outline Dimensions
HD D
100 81
Unit: Inches/mm
1
80
30 31 50
51
GE
HE
E
F
GD ~ ~ ~ c A2 A1 A
e GD
b
See Detail F Seating Plane
y
D
L L1
Detail F
Symbol A A1 A2 b c D E e F GD GE HD HE L L1 y
Dimensions In Inches 0.130 Max. 0.004 Min. 0.1120.005 0.012 +0.004 -0.002 0.006 +0.004 -0.002 0.5510.005 0.7870.005 0.026 0.006 0.742 NOM. 0.693 NOM. 0.929 NOM. 0.7400.012 0.9760.012 0.0470.008 0.0950.008 0.006 Max. 0 ~ 12
Dimensions In mm 3.30 Max. 0.10 Min. 2.850.13 0.31 +0.10 -0.05 0.15 +0.10 -0.05 14.00+/-0.13 20.00+/-0.13 0.650.15 18.85 NOM. 17.60 NOM. 23.60 NOM. 18.800.31 24.790.31 1.190.20 2.410.20 0.15 Max. 0 ~ 12
Note:
1. Dimension D & E do not include resin fins. 2. Dimension GD & GE are for PC Board surface mount pad pitch design reference only. 3. All dimensions are based on metric system.
Final Version: DM9301-DS-F02 May 8, 2000
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DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Ordering Information
Part Number DM9301F Pin Count 100 Package QFP DAVICOM `s terms and conditions printed on the order acknowledgment govern all sales by DAVICOM. DAVICOM will not be bound by any terms inconsistent with these unless DAVICOM agrees otherwise in writing. Acceptance of the buyer's orders shall be based on these terms.
Disclaimer
The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, DAVICOM MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. DAVICOM reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by DAVICOM for such applications. Please note that application circuits illustrated in this document are for reference purposes only.
Company Overview
DAVICOM Semiconductor, Inc. develops and manufactures integrated circuits for integration into data communication products. Our mission is to design and produce IC products that are the industry's best value for Data, Audio, Video, and Internet/Intranet applications. To achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements.
Products
We offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. Our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and Ethernet networking standards.
Contact Windows
For additional information about DAVICOM products, contact the sales department at: Headquarters Hsin-chu Office: 3F, No. 7-2, Industry E. Rd., IX, Science-based Park, Hsin-chu City, Taiwan, R.O.C. TEL: 886-3-5798797 FAX: 886-3-5798858 WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function.
Taipei Sales & Marketing Office: 8F, No. 3, Lane 235, Bao-chiao Rd., Hsin-tien City, Taipei, Taiwan, R.O.C. TEL: 02-29153030 FAX: 02-29157575 Email: sales@davicom.com.tw
Davicom USA Sunnyvale, California 1135 Kern Ave., Sunnyvale, CA94086, U.S.A. TEL: 1-408-7368600 FAX: 1-408-7368688 Email: sales@davicom8.com
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Preliminary Version: DM9301-DS-F02 May 8, 2000

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